(10-03-2017, 11:11 AM)gto4ben Wrote: (10-03-2017, 12:27 AM)gunnard Wrote: (10-03-2017, 12:06 AM)gto4ben Wrote: (10-02-2017, 11:46 PM)gunnard Wrote: (10-01-2017, 11:06 AM)gto4ben Wrote: I changed the Intel RAID OROM only so you can use HDs >3TB. I'll leave everything else stock since some users had difficulty with those changes for this motherboard.
Modified GA-EP45T-UD3LR rev 1.0 F12e bios with the following changes:
Intel RAID - v11.2.0.1527 Intel RAID with trim. This version is stable and is fast with the raid chipset used on these motherboards. I personally use it myself.
Let us know how this one works out.
Genius!! Thank you so much! I´m gonna test it and tell you about the stability. Notice that my mobo is EP45T and support DDR3 memories, is it the same?
Do you know what kind of changes we need to be able to run windows 10 in this motherboard? I've read that the UEFI BIOS is the essential
The file in the attachment is correct for the ga-ep45t-ud3lr which is your motherboard. Thanks for catching the typo. Windows 10 will run fine on your motherboard without an UEFI bios. If in doubt, try the Win10 upgrade evaluation that checks if it can run Win10.
Great! i gonna test it now! I tried to install Win10 and had this problem: CMPXCHG16b / CompareExchange128. So it will be the Xeon X5460 that I'm using in this mobo. Is there any solution to this? Maybe something about the microcodes?
I downloaded and executed in a CMD line "coreinfo.exe" and it shows my Xeon X5492 supports CX16 which is for the CMPXCHG16B instruction. This explains why I did not see a problem. It also correctly identified the CPU as a X5492. Execute "coreinfo" on your machine and see if it correctly shows a X5460. If it shows another CPU, then a microcode update in the bios is needed. I tried a microcode update for your motherboard once but another user had problems. If you can solve your 3TB problem first, let me know and I'll update the microcodes for you to try. Just be prepared to perform a recovery from your motherboards backup bios just in case.
Thank you! I have this information from coreinfo:
C:\Windows\system32>c:\coreinfo.exe
Coreinfo v3.31 - Dump information on system CPU and memory topology
Copyright © 2008-2014 Mark Russinovich
Sysinternals -
www.sysinternals.com
Intel® Xeon® CPU X5460 @ 3.16GHz
Intel64 Family 6 Model 23 Stepping 10, GenuineIntel
Microcode signature: 00000A0B
HTT * Hyperthreading enabled
HYPERVISOR - Hypervisor is present
VMX - Supports Intel hardware-assisted virtualization
SVM - Supports AMD hardware-assisted virtualization
X64 * Supports 64-bit mode
SMX - Supports Intel trusted execution
SKINIT - Supports AMD SKINIT
NX * Supports no-execute page protection
SMEP - Supports Supervisor Mode Execution Prevention
SMAP - Supports Supervisor Mode Access Prevention
PAGE1GB - Supports 1 GB large pages
PAE * Supports > 32-bit physical addresses
PAT * Supports Page Attribute Table
PSE * Supports 4 MB pages
PSE36 * Supports > 32-bit address 4 MB pages
PGE * Supports global bit in page tables
SS * Supports bus snooping for cache operations
VME * Supports Virtual-8086 mode
RDWRFSGSBASE - Supports direct GS/FS base access
FPU * Implements i387 floating point instructions
MMX * Supports MMX instruction set
MMXEXT - Implements AMD MMX extensions
3DNOW - Supports 3DNow! instructions
3DNOWEXT - Supports 3DNow! extension instructions
SSE * Supports Streaming SIMD Extensions
SSE2 * Supports Streaming SIMD Extensions 2
SSE3 * Supports Streaming SIMD Extensions 3
SSSE3 * Supports Supplemental SIMD Extensions 3
SSE4a - Supports Streaming SIMDR Extensions 4a
SSE4.1 - Supports Streaming SIMD Extensions 4.1
SSE4.2 - Supports Streaming SIMD Extensions 4.2
AES - Supports AES extensions
AVX - Supports AVX intruction extensions
FMA - Supports FMA extensions using YMM state
MSR * Implements RDMSR/WRMSR instructions
MTRR * Supports Memory Type Range Registers
XSAVE - Supports XSAVE/XRSTOR instructions
OSXSAVE - Supports XSETBV/XGETBV instructions
RDRAND - Supports RDRAND instruction
RDSEED - Supports RDSEED instruction
CMOV * Supports CMOVcc instruction
CLFSH * Supports CLFLUSH instruction
CX8 * Supports compare and exchange 8-byte instructions
CX16 - Supports CMPXCHG16B instruction
BMI1 - Supports bit manipulation extensions 1
BMI2 - Supports bit manipulation extensions 2
ADX - Supports ADCX/ADOX instructions
DCA - Supports prefetch from memory-mapped device
F16C - Supports half-precision instruction
FXSR * Supports FXSAVE/FXSTOR instructions
FFXSR - Supports optimized FXSAVE/FSRSTOR instruction
MONITOR - Supports MONITOR and MWAIT instructions
MOVBE - Supports MOVBE instruction
ERMSB - Supports Enhanced REP MOVSB/STOSB
PCLMULDQ - Supports PCLMULDQ instruction
POPCNT - Supports POPCNT instruction
LZCNT - Supports LZCNT instruction
SEP * Supports fast system call instructions
LAHF-SAHF * Supports LAHF/SAHF instructions in 64-bit mode
HLE - Supports Hardware Lock Elision instructions
RTM - Supports Restricted Transactional Memory instructions
DE * Supports I/O breakpoints including CR4.DE
DTES64 - Can write history of 64-bit branch addresses
DS * Implements memory-resident debug buffer
DS-CPL - Supports Debug Store feature with CPL
PCID - Supports PCIDs and settable CR4.PCIDE
INVPCID - Supports INVPCID instruction
PDCM - Supports Performance Capabilities MSR
RDTSCP - Supports RDTSCP instruction
TSC * Supports RDTSC instruction
TSC-DEADLINE - Local APIC supports one-shot deadline timer
TSC-INVARIANT - TSC runs at constant rate
xTPR - Supports disabling task priority messages
EIST - Supports Enhanced Intel Speedstep
ACPI * Implements MSR for power management
TM * Implements thermal monitor circuitry
TM2 * Implements Thermal Monitor 2 control
APIC * Implements software-accessible local APIC
x2APIC - Supports x2APIC
CNXT-ID - L1 data cache mode adaptive or BIOS
MCE * Supports Machine Check, INT18 and CR4.MCE
MCA * Implements Machine Check Architecture
PBE * Supports use of FERR#/PBE# pin
PSN - Implements 96-bit processor serial number
PREFETCHW * Supports PREFETCHW instruction
Maximum implemented CPUID leaves: 0000000D (Basic), 80000008 (Extended).
Logical to Physical Processor Map:
*--- Physical Processor 0
-*-- Physical Processor 1
--*- Physical Processor 2
---* Physical Processor 3
Logical Processor to Socket Map:
**** Socket 0
Logical Processor to NUMA Node Map:
**** NUMA Node 0
No NUMA nodes.
Logical Processor to Cache Map:
*--- Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
*--- Instruction Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
-*-- Data Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
-*-- Instruction Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
**-- Unified Cache 0, Level 2, 6 MB, Assoc 24, LineSize 64
--*- Data Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64
--*- Instruction Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64
---* Data Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64
---* Instruction Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64
--** Unified Cache 1, Level 2, 6 MB, Assoc 24, LineSize 64
Logical Processor to Group Map:
**** Group 0